1. Field of the Invention
The invention relates to the field of electrostatic discharge (ESD) protection circuits and in particular to a low loading capacitance on-chip electrostatic discharge (ESD) protection circuit for compound semiconductor (such as GaAs, InP, SiGe etc) heterojunction bipolar transistor RF circuits.
2. Description of the Prior Art
Compound semiconductor heterojunction bipolar transistors (HBT) are attractive for RF integrated circuits (RFIC). For example, due to the high electron mobility, high current gain, low base resistance, and low loss semi-insulated substrate, a GaAs heterojunction bipolar transistor is advantageous for high frequency and high power application, such as power amplifiers for hand held phones. Even with a 2 μm width, GaAs heterojunction bipolar transistors have unity current gain bandwidth of 40 GHz and a maximum oscillation frequency of 90 GHz. In addition, high Early voltage, high breakdown voltage, and low knee voltage of this technology are ideal for power amplifiers for high output power and good linearity.
A GaAs heterojunction bipolar transistor is fabricated on a GaAs semi-insulated substrate. The epitaxy active layers of the heterojunction bipolar transistor are grown on the substrate using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) as shown in FIG. 1. For the ESD protection circuit, a diode is a common component. Because the GaAs diode is epi-grown on a semi-insulated substrate, the diode does not have a leakage problem like the silicon diode. The thin epitaxy active layers are prone to damages from an ESD event. To reduce chip loss due to ESD events during human and machine handling, on-chip ESD protection circuit is needed.
The ESD protection circuit should have low capacitance loading so the circuit RF performance is not affected. The capacitance loading from the ESD protection circuit can affect power gain, linearity, and bandwidth.
An ESD protection circuit is comprised of a positive threshold voltage clamp and a negative threshold voltage clamp. Each clamp turns on and sinks the ESD current at a preset voltage. The positive threshold voltage clamp design should take into consideration the voltage swing of the signal, whereas the negative threshold voltage clamp does not need such a requirement. The positive threshold voltage clamp must be designed to sink ESD current at a preset voltage, while the negative threshold voltage clamp can be designed to sink ESD current at any voltage before device breakdown. The negative threshold voltage clamp simply can be a reverse diode.
Among various RF circuits, power amplifiers have stringent design requirements in both ESD protection and RF performance. In this invention, the ESD protection circuit is designed to meet such requirements and can be also used in other RF circuits. The current ESD protection circuit used by the GaAs power amplifier community is a diode string 10 as shown in FIG. 2. This ESD protection circuit consists of a diode string 10 and a reverse diode 12. During a positive ESD surge, the diode string 10 turns on and sinks the ESD current. The number of diodes in the string 10 determines the headroom allowed for the signal. Eight diodes are shown here for 10V headroom operation. During a negative ESD surge, the reverse diode 12 turns on and sinks the ESD current. The major drawback of the ESD protection circuit of FIG. 2 is that the size of the diodes in the string 10 needs to be big in order to reduce the parasitic resistance.
FIG. 3 illustrates this problem by a low frequency model of this ESD protection circuit during a positive ESD surge. For low frequency, the diode string 10 can be represented by a series of resistors 10′ during a positive ESD surge; the resistance value is inversely proportional to the area of the diode in string 10. The resistance value of the diode in string 10 is typically 3.7 ohm for a 100 μm2 emitter area. During a 2KV ESD event, approximately 1.3 Amp of ESD peak current sinks through the series resistors 10′. Because of this significant amount of ESD peak current sunk through the resistance 10′, the pad voltage might be well over the breakdown voltage of the active devices in the main circuits.
FIG. 4 shows clamping voltage for an 8-diode string 10 versus diode size for a +2000VESD. To have an acceptable clamping voltage, the size of each diode required is 1600 μm2, which takes up too large an area. Currently in the power amplifier community, diode size of 100 μm2 is used for the diode string 10. The small size is necessary because of smaller chip area and lower capacitance loading. For this diode size, the diode string 10 can protect against only about 200VESD.
What is needed is an ESD protection circuit and methodology which is not subject to these limitations of the prior art.